The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A FET includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions. The FETs are generally “N” or “P” type FETs, (“nFET” or “pFET”) where the source and drain for nFETs are implanted with “N” type conductivity-determining ions, and the source and drain for pFETs are implanted with “P” type conductivity determining ions.
The gate electrode may be a replacement metal gate, or simply a metal gate. A sacrificial gate, which is called a “dummy” gate, is initially formed while other components of the integrated circuit are manufactured. The “dummy” gates for the pFETs are typically removed and replaced with a replacement metal gate first, and then the “dummy” gates for the nFET are removed and replaced with the replacement metal gate. However, the “dummy” gates can be replaced in the opposite order, where the nFET is replaced first. Overburden from the formation of the metal gates is removed by chemical mechanical planarization, (referred to herein as “planarization.”) Therefore, the metal gate formed first is planarized twice; once after the formation of each type of metal gate. The planarization process reduces the gate height, and the amount of gate height reduction is variable. The reduction in gate height increases the electrical resistance in the gate and changes a threshold voltage for the FET in a variable and unpredictable manner. Electric circuit models may not be accurate when the gate resistance or the threshold voltage for a transistor are not within a specified range, so the reliability of the integrated circuit can be reduced.
Accordingly, it is desirable to provide integrated circuits and methods of manufacturing integrated circuits with more consistent metal gate heights. In addition, it is desirable to provide integrated circuits and methods of forming them with higher metal gate heights, especially for the metal gates formed first. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.